
%\vspace{-15pt}
\section{Conclusion}\label{sec:conclusion}

This paper presents a two-stage thermal management technique on design-time and run-time to solve the thermal challenges on 3D architectures. The design-time TSV thermal stress-aware placement technique aims at reducing the TSV thermal load during placement at design time. During the run time, the mechanical reliability challenges of thermal gradients and thermal cycling pattern are considered. Controlling the temperature gradients and eliminating damaging thermal cycling patterns can reduce the risk of cracking on the thinned silicon substrate. The results show that design-time placement can effectively reduce TSV thermal load for thermomechanical stresses minimization. The radical thermal stress reductions on average is 18.43MPa in unit-level and 19.03MPa in core-level case studies. After run-time management, the core to memory stacking can achieve mechanical equilibrium on thermal cycling through dynamic power scaling.